In article you write: > Following the enthusiasm shown by many on this group who seem to be > "in the know," I've been looking into the Titan III motherboard. > I've decided not to get one, nor to get any other board based on > the current Triton chipset. Here're my reasons why: > >In article , >jhurwit@netcom.com (Jeffrey Hurwit) wrote: > > [quoted from an e-mail from support@tyan.com] > >>1. No, the ECC is only availible on the Triton 2 chipset and Intel will >>not sell those chipset until next year. And No, Triton 1 chipset does not >>have the ECC function. >>2. The triton 1 chipset's cache cycle is fixed at 311111. > > 1) There was some recent discussion in this group about the new Triton > II chipset, centering around its ECC (Error Correction Circuitry) > feature. The discussion ended abruptly in a way that left me > thinking that the chipset had been released, and that it was being > used in the latest boards. It has not. This means that all > current Triton-based boards (including the Titan III and Supermicro > P55) do NO error checking in memory of any kind (except for the > POST, of course). If error checking is important to you (and it is > to me), these latest high-performance boards are no better than any > other Triton-based board. If you feel that memory error is no > longer a significant risk, then this is of course no concern to > you. > > I spoke on the 'phone with a customer service rep at Intel, and he > confirmed that Triton II would not be released until sometime next > year. He said that Intel had not scheduled a release date, and he > declined to "guesstimate" on when it might be released. He > suggested Intel's P6 (which Intel now calls 'Pentium Pro') chipset, > 82450GX and 82450KX, which he said does support ECC. He said that > the Pentium Pro and related products were released Nov. 1 of this > year. > > 2) Someone already wrote in this group that the current Triton chipset > doesn't support the 2-1-1-1 cycle of Synch Burst cache. support > @tyan.com confirmed this. Your options with the Triton chipset are > Asynch cache, or 3-1-1-1 Pipeline Burst cache. > > 3) Additionally, Patrick Duffy has this to say in his PCI Chipsets > list (see particularly the section on limitations): > > Document: PCI chipsets list > Maintainer: Patrick Duffy, duffy@theory.chem.ubc.ca >Last Revision Date: October 31, 1995 > Archived at: ftp.netcom.com, in directory /pub/ab/abe/ > CompuServe (GO BENCHMARK) > Web pages: http://warp.eecs.berkeley.edu/os2/workbench/work.htm > http://www.os2forum.or.at/english/info/os2hardwareinfo/ > (note that the first URL may not have up-to-date > versions of the lists) > >This document is intended for use by individuals and corporations in a >non-commercial manner. It may be distributed freely within those >limitations. Commercial use of this document in any manner requires >prior written permission of the author. > >Here follows a brief summary of PCI chipsets. I've tried to keep it >accurate, but if you spot any flaws please feel free to correct me, and >if you have details on other chipsets, please feel free to let me know >about them. I've included information at the end of this list to help >people ID the chipset (assuming they have an Intel chipset on their >motherboards). Where I know for sure that they do, I have indicated >that a chipset will use parity RAM. PCI Vendor IDs first in HEX then in >decimal appear in brackets beside the chipset names. Dates in brackets >indicate the last revision date of the related entry. > > New This Week: > -------------- > >Well, it looks like the Triton chipset (version 1) isn't quite the >high-performance dream that we all thought it would be when hooked up to >an IDE drive in a multitasking O/S. Check out the Triton entry for >further details (why does _ANYONE_ buy IDE anymore...). I've also added >the part numbers for the Triton chipset. Maybe Triton II (due out >sometime soon) will fix all the limitations in Triton I. See below for >a tentative listing of Triton II features. > > > >10) The Triton Chipset (Intel: 8086/32902) (9/21/95) > ------------------ > >Components: 82437FX System Controller > 82438FX Data Path > 82371FB PCI ISA IDE accelerator > >This is the latest PCI chipset to come out from Intel, and is PCI >2.1-compliant. It will also increase PCI-to-memory bandwith from 40 >MB/sec (in Neptune) to 100 MB/sec, and features an enhanced ISA bridge >and built-in EIDE support. Drivers for all major operating systems to >take advantage of the busmastering capability of the Triton chipset may >be found in the file called triton.exe (or triton.zip), available at >all the major OS/2 FTP sites. (Note that one person has reported that his >system locks when using this driver in combination with fixpack 9). It >also supports EDO RAM, which will allow access to RAM in a 3-2-2-2 burst >rather than the conventional 7-4-4-4 burst. There is also now a 12 word >buffer between the PCI bus and memory as opposed to the 8 word buffer in >Neptune. The chipset does not check parity, although parity RAM may be >used (without any benefit) in systems which use the chipset. Systems >which use the chipset appear to run OS/2 very well. > >It would seem that there may be (soon if there isn't already) more than >one version of this chipset. Early versions of the chipset are reported >to have (unspecified) problems with Matrox and (some) Diamond Stealth >cards. (These problems appear to be video card-related and nothing to >do with Triton.) > >Chipset limitations: >-------------------- > >Triton I will not cache more than 64 MB of RAM. Triton I also has the >following (rather serious) drawback when its IDE features are used in a >multitasking environment (this paraphrased from the Intel spec.): > >First of all, the Triton chipset has only a single bus for its two IDE >channels. This means that only one IDE device may be active at a time, >even if you have them on separate channels. Second, it also shares this >data bus with the ISA address/data bus function that is also in the >chip. This means that if you have your serial or parallel ports on the >Triton ISA bus (as most motherboard designs do) and you have any COM or >LPT activity going on this will be multiplexed with your two ATA >interfaces on the same set of signals comming out of the Triton chip. >This could really bring multitasking to a crawl if you have a >disk-intensive program going and you're trying to download something in >the background (or, for that matter, even use a serial mouse). Intel >claims "fair round robin" sharing of all the uses of the single bus, >however. > >11) The Triton II Chipset (Intel: 8086/32902) (9/21/95) > >This chipset, according to a source at AMI, is not so much a revision >level of Triton I but a redesign of the Neptune chipset. The newest >Triton chipset will support: > >1) Caching of RAM up to 512 MB. >2) Support for SMP (up to 4 processors). >3) Support for parity/ECC RAM. > >There are probably more features to be added, but that's what I know >now. I do not know if the IDE/ISA limitation listed above for Triton I >will be removed in this version. > > [End quoted section.] > > Jeff